The invention relates to inspection technology and in particular to inspection of a piping defect inducing short circuit in a semiconductor device.
As the integrity of integrated circuits increases, the size of semiconductor device is reduced. In interconnection technology of an IC, for example, boron phosphosilicate tetra-ortho-silicate (BPTEOS) is typically utilized as a dielectric layer. When the line width is reduced to approximately 0.18 μm or less, piping defects occur frequently, negatively affecting the process yield.
FIGS. 1 through 3, 4A, and 4B show generation of a piping defect during an interconnection process for a semiconductor device.
In FIG. 1, first, a substrate 100, such as single crystalline silicon, comprising a transistor structure, is provided. The substrate 100 comprises a plurality of source/drain regions 132 individually arranged on an active surface of the substrate 100. The substrate 100 comprises isolation regions 110 respectively disposed between the source/drain regions 132 along direction Y in FIG. 1. The substrate 100 comprises a plurality of gate electrodes 120 protruding from the active surface thereof between the source/drain regions 132 along direction X in FIG. 1. The gate electrodes 120 typically comprise multi-layer structures comprising conductive layers as desired. The gate electrodes 120 comprise spacers 126 on sidewalls thereof, and thus, the exposed source/drain regions 132 between two spacers 126 of two neighboring gate electrodes 120 are typically less than 0.15 μm wide when the line width is reduced to approximately 0.18 μm or less by design rule of the semiconductor device.
In FIG. 2, a blanket dielectric layer 140, acting as a pre-metal dielectric layer, is formed overlying the substrate 100. The blanket dielectric layer 140 is shown transparently for subsequent description. A piping defect 145 extending across at least two source/drain regions 132 appears in dielectric layer 140 during formation thereof using BPTEOS when the design rule is reduced to less than about 0.18 μm.
In FIG. 3, the dielectric layer 140 is patterned to form vias 142 exposing the source/drain regions 132. Simultaneously, the former piping defect 145 becomes piping defect 145′ connecting two neighboring vias 142.
In FIG. 4A and FIG. 4B, cross-sections along line AA in FIG. 4A, the vias 142 are respectively filled with a conductive layer, and thus, plugs 162a through 162c are formed respectively connecting to the corresponding source/drain regions 132. Simultaneously, the piping defect 145′ is also filled with the conductive layer. Thus, the plugs 162a and 162b, intended to be electrically isolated by the isolation regions 110 and dielectric layer 140 in design, bridge via the piping defect 145′, inducing short circuit.
The piping defect 145′ cannot be identified by naked eye or optical microscope due to typically deep embedment in the dielectric layer 140. Conventionally, the piping defect 145′ is detected by wafer probing after completion of the wafer fabrication process. Alternatively, the piping defect 145′ can be detected by sample destructive testing after formation of the dielectric layer. The destructive testing is performed by removal of the dielectric layer 140 to expose the plugs 162a through 162c utilizing an etchant or etch method with high etch selectivity of the dielectric layer 140 to the plugs 162a through 162c. Thus, the piping defects between the plugs 162a through 162c are identified by SEM.
The period between the formation of the conductive layer and wafer probing, however, can be between two and three months. Discovery of piping defects in wafer probing indicates occurrence of the piping defect potentially during the two to three months, affecting the process yield. Further, shutdown, check, and repair of the production line, and overall inspection for the products are required, and thus, internal failure cost increases substantially.
When destructive testing is performed, the sampling unit is per piece of wafer. These sacrificed wafers increase the product loss.